1. Field of the Invention
This invention relates to a data processor with the function of synchronizing a plurality of chips. The invention, which is applied to, for example, a color digital complex machine, is useful as an application specific integrated circuit (ASIC) used in configuring an image forming apparatus with the function of putting the phases of the image data outputs of a plurality of colors in phase, for example, an image processing integrated circuit (ASIC).
2. Description of the Related Art
A color digital complex machine has a read unit for reading a document. The output of the read unit is treated as R (red), G (green), and B (blue) image data at the image processing section. These RGB image data are synchronized with one transfer clock. The RGB image data are subjected to image processing as needed and are eventually converted into C (cyan), M (magenta), Y (yellow), and K (black) image data, which are then sent to the print section. According to the CMYK image data, the print section controls the printer driver, thereby printing out color images.
In such an image processing section, when RGB image data or CMYK image data are subjected to image processing, the image data of the individual colors synchronize with the same clock, as long as they are processed in one IC. Even when the individual colors are allocated to separate ICs, the image data of the individual colors synchronize with the same clock, as long as the ICs of the individual colors synchronize with the same external clock.
In recent years, however, image processing has been complicated because of an increase in the picture quality. As a result, in the RGB image data processing section or YMCK image data processing section, the size of the image processing block of each color tends to become enlarged. In addition, when image data of three colors of RGB or image data of four colors of YMCK are processed, only one image processing ASIC sometimes cannot include all of the necessary circuits for the processing. As a result, the image data have to be divided into pieces of image data to be processed on a one-color basis or a two-color basis and then independent image processing ASICs have to be provided so as to correspond to the divided pieces of image data.
Furthermore, the image processing sections have been strongly requested not only to produce higher-quality pictures but also to operate at higher speed. To increase the processing speed, each of the image processing ASICs has been requested to use a PLL (Phase Locked Loop) oscillator in it, thereby making the internal operation clock faster.
With the recent requests for higher-quality pictures and higher speed, the image processing ASICs may be divided on a color basis and further each of the image processing ASICs may use a PLL oscillator in it.
However, there are variations in time in the image processing ASIC of each color until the PLL oscillator supplies a stable clock to the image processing ASIC. Thus, the internal operation clocks can be desynchronized with one another color by color.
In such a case, since the image data of the individual colors output to the processing section at a subsequent stage are asynchronous with one another, they have to be synchronized with one another again when image processing is performed using a plurality of colors at the processing section at a subsequent stage.
If the processing section at a subsequent stage has the function of synchronizing the individual color image data, there is no problem. However, it does not have the synchronizing function, the individual image data are desynchronized with one another at the processing section at a subsequent stage, with the result that image processing cannot be performed.
Furthermore, the image data of each color is stored temporarily in such a memory as a page memory and the data of each color is read out in synchronization with one clock, which enables the image data of a plurality of colors to be output in synchronization with one clock. To achieve this, a memory must be added, resulting in an increase in the cost. These problems are encountered not only in the RGB images read by the read unit but also in a case where the RGB/YMCK image data are output by external image data output means to the color digital complex machine.